1. Field of the Invention
The present invention generally relates to a sampling phase technique of an analog-to-digital converter and phase lock loop (ADC-PLL), and more particularly, to a sampling phase technique where a number of motion data between periodic digital signals (e.g., texture images) is used as the calibration base of the sampling phase.
2. Description of Related Art
When an ADC-PLL is sampling, it would be interfered by clock jitter, which further affects the quality of the obtained digital signal. Hence, it is needed to calibrate the sampling phase of the ADC-PLL so as to correctly sample analog signals.
FIG. 1 is a diagram showing the influence of clock jitter on the sampling of an ADC-PLL in the prior art. Referring to FIG. 1, an ADC-PLL conducts sampling on an analog signal of FIG. 1. Assuming the ADC-PLL samples once per a duration T0-T1 on an analog signal S, the ADC-PLL in the embodiment has four sampling phases ph1, ph2, ph3 and ph4. If the ADC-PLL is in an ideal status (i.e., no clock jitter), the ADC-PLL can exactly conduct sampling at the point DA1, DA2, DA3 or DA4 according to one of four sampling phases, i.e., according to one of the sampling phase ph1, the sampling phase ph12, the sampling phase ph3 or the sampling phase ph4. In fact, due to the interference of clock jitter, taking the sampling phase ph1 as an example, the ADC-PLL may sample a point between the highest sampling point DA1H and the lowest sampling point DA1L in a range D1, not the expected sampling point DA1. Analogically for the rest, when the ADC-PLL samples the analog signal S according to the sampling phase ph2, ph3 or ph4, the sampled point might be any one point in the range D2, D3 or D4. Since the information variation in the range D1 is smaller, the variation of the digital information obtained after the sampling is accordingly smaller. However, in the range D2, D3 or D4, the information variation may be excessive so that the variation of the digital information obtained after the sampling is too large to conduct a better sampling on the analog signal S. Hence, the sampling phase of the ADC-PLL should be calibrated to get an optimal sampling phase ph1 by the sampling phase calibration technique so as to reduce the influence of clock jitter during sampling to the minimum.
In the conventional sampling phase calibration technique, every sampling phase is used to conduct sampling, and a sampling phase corresponding to the maximum sum of absolute difference (SAD) between the sampling results serves as the optimal sampling phase. However, when the clock jitter is larger, the above-mentioned optimal sampling phase in the prior art would lead to incorrect sampling or instability of the sampling quality.